Project Update

Since the previous post this is what I have worked on:

1. Modifying the UVM components to be more generalized and flexible 
2. Found a data corruption bug in the FIR filtering block
3. Found an integration bug where I had a typo on a port name

Modifying UVCs

Improving the "UVCs" has taken much longer than I anticipated. The DUT has different data widths for the input signals vs the output signals. At first I thought I could simply cast a parameterized interface and pass that to the testbench using uvm_config_db. I quickly learned that this wasn't going to work. Someone else on the internet had exactly the same problem. I used solution #2 as suggested in that form. I needed to parameterize the low-level testbench components that use the virtual interface. After making the changes and fixing the bugs I introduced in the process it seems to work well. Not only did monitor and driver components need to be modified but the sequence items needed to be changed to use dynamic arrays to be more flexible.

Previously the sample interface agent was well developed to be a SLAVE device because that was the only requirement for the previous DUT. The current DUT has a SLAVE and MASTER interface. Some development effort was required to get that aspect operational.

What's Next?

I was debugging a DUT bug in the filtering sub-block but time ran out. I will pick it up next weekend. I think I have done the majority of the ground work needed so i can start working on the scoreboard next weekend. Lets see how it goes!