My New Project

In my last post I discussed how the "autotune" pitch correction projects was taking too much effort outside of the core skills that I wanted to practice.

I've decided to start working on verification of the OpenRISC cores. This way I can completely focus on the DUT.  I am going to start on the OR1200 core as it seems stable and not under active development anymore.  This feels like the best project to increase my chances of breaking into the hardware verification field.  CPU verification is one of the more common opportunities I've recently seen for verification engineers and many companies are deciding to use their own CPU solutions which require their own verification efforts.

The OpenRISC community seems to be very active and accessible which is an important factor.  This project idea is great because I can start with block verification, move to full CPU verification and even do verification efforts at the SoC level.  There is an existing set of tools for verification at the different levels but I am going to write my own because I will be able to refresh on my UVM skills while getting familiar with CPU designs.

I've been browsing through the OR1200 spec and the HDL.  The first obvious course of action is to develop the verification tools around the Wishbone interface.  In OR1200 wishbone is used for the CPU to access main memory.

The Wishbone specification is well documented and there are some HDL BFMs on github so it will help me rampup.  I plan to write a SystemVerilog/UVM testbench for this. The interface will have SystemVerilog Assertions to catch protocol violations and the UVM components will be capable of sending and receiving Wishbone transactions.

Ill update once i have something to share.