Step Zero for or1200_uvm

Here is the quick update and summary:

1. I setup my development machine using Amazon AWS (EC2)
2. I started reading the documentation for the the or1200 processor
3. I've selected my first interface to target
4. Finally created an account at github

Based on my reading of the or1200 processor it uses a wishbone interface to reach imem (instruction memory) and dmem (data memory). The wishbone interface is heavily used in open source hardware designs. I don't want to get too far ahead of myself but... If I complete a functional verification environment for the or1200 processor then the next step would be SOC level verification. My limited understanding says that most peripherals use the wishbone interface also.

So I've concluded that a worthy first task is to invest the effort into making an extremely robust wishbone uvm_agent. I am going to have an agent that has API for all of the low level transactions then a testbench/testcase developer can write more complicated protocols on top of my implementation. I also want to take the opportunity to apply my SystemVerilog Assertions course knowledge in the wishbone interface to verify low-level protocol correctness. As of this post I am still laying-out the "boiler plate" UVM structure but I hope to eventually have a functional MASTER to SLAVE loopback type of test up and running.

I'll continue to post as I make progress.