Pitch Correction Project Update - 10/19

I have to apologize in advance because I don't spend enough time putting these posts together. I want to tell a clear story but at the same time - every minute spent on the post is a minute not spent on the project.

ADC Controller Off By 1 issue

 I fixed the off by 1 issue. The root cause was because I started decrementing the index counter 1 cycle too early. As a work around I simply had a local chip select signal that was delayed by 1 clock cycle. When the decrement logic was triggered by the delayed signal things began to look better.

As I was fixing the off by 1 issue I found another issue where I wasn't recording the LSB of the sample before sending it out to the next section of the design. I didn't even bother trying to fix this because I realized I needed to rewrite the block. More details in the next section

ADC Controller Rewrite

When writing the RTL for the ADC controller I assumed could get desired sample rate by using the "single shot" method. In the single shot method the chip select signal is only asserted for a single sample retrieval. As I was debugging I realized that consecutive "single shots" were not going to give the desired sample rate. I would have to use the ADC in it continuous sampling mode. The first implementation was a mess because it was my RTL coding refresher. I scrapped the first implementation and recoded it. This time it only took fraction of the time to code the block and it worked after fixing a few basic typos. Nice!

Scoreboard for ADC_to_Samples block

On the verification side of the project I completed the scoreboard for the ADC_to_samples block. I have been working on the verification infrastructure for this block for a couple of weeks. Now the first alpha verification environment is complete and it seems to be working.

Up Next: Interpolation filter

Now that that ADC_to_samples block is "complete" I can move to the next block in the project. I'm taking a simple strategy of following the data path. The next next block is the interpolation filter. I included an interpolation filter to try to compensate for the poor ADC resolution (12 bits). I hope that I can sample at the ADC max sample rate (200 ksps) and use the interpolation filter for sample smoothing and moving down to 44.1ksps.

This block should be a lot more interesting than the adc_to_samples  block because it will force me to refresh on fixed point arithmetic, filter structures and the verification side will be far more involved WRT the scoreboard.

The only spec I have for the block is at the interface level so I need to begin the functional decomposition process until I have more manageable design components.

Lets see how it goes!