Project Update

This weekend I started working on the re-sampling block. The "zeroth draft" of the RTL for the zero stuffing block is complete. I will also share the pre-first draft of the spec for the block to show the design intent. This weekend I didn't get a chance to start the RTL for the  filtering block but I have been putting in a lot of mental effort, visualizing how the logic should work (inferred hw multipliers etc). I'm leaving the filtering block for next weekend.

The Block Diagram for the re-sampling block

Zero Stuffing

Module	Zero Stuffing
Inputs	sample_valid_i : active high signal that the slave device uses to determine when the value on the sample bus is valid [11:0] sample_i : the sample data to be read by the slave device sample_rdy_filter_to_zs : active high signal that the master device uses to determine if the slave is ready to receive a sample sample_ack_filter_to_zs : active high signal that the master device uses to determine if the slave successfully received the sample rst : synchronous, active high reset signal en : synchronous, active high enable signal clk : system clock
Outputs	sample_rdy_i : active high signal that the slave device uses to indicate it is ready to receive a sample sample_ack_i : active high signal that the slave device uses to indicate that the sample has been successfully received sample_valid_zs_to_filter : active high signal that the master device uses to indicate that the signal on the sample bus is valid [11:0] sample_zs_to_filter : the sample data written by the master devices
Functionality	To achieve an interpolation factor of 6 the first step is zero stuffing. 5 zero samples are appended for every original sample.

<write up>

Filtering

Module	Filtering
Inputs	sample_valid_zs_to_filter : active high signal that the slave device uses to determine when the value on the sample bus is valid [11:0] sample_zs_to_filter : the sample data to be read by the slave device sample_rdy_dec_to_filter : active high signal that the master device uses to determine if the slave is ready to receive a sample sample_ack_dec_to_filter : active high signal that the master device uses to determine if the slave successfully received the sample rst : synchronous, active high reset signal en : synchronous, active high enable signal clk : system clock
Outputs	sample_rdy_filter_to_zs : active high signal that the slave device uses to indicate it is ready to receive a sample sample_ack_filter_to_zs : active high signal that the slave device uses to indicate that the sample has been successfully received sample_valid_filter_to_dec : active high signal that the master device uses to indicate that the signal on the sample bus is valid [35:0] sample_filter_to_dec : the sample data written by the master devices
Functionality	The filtering block has two roles: Interpolation filtering Lowpass filtering to prevent aliasing before decimation

<write up>

Decimation

Module	Decimation
Inputs	sample_valid_filter_to_dec : active high signal that the slave device uses to determine when the value on the sample bus is valid [35:0] sample_filter_to_dec : the sample data to be read by the slave device sample_rdy_rs_to_dec : active high signal that the master device uses to determine if the slave is ready to receive a sample sample_ack_rs_to_dec : active high signal that the master device uses to determine if the slave successfully received the sample rst : synchronous, active high reset signal en : synchronous, active high enable signal clk : system clock
Outputs	sample_rdy_dec_to_filter : active high signal that the slave device uses to indicate it is ready to receive a sample sample_ack_dec_to_filter : active high signal that the slave device uses to indicate that the sample has been successfully received sample_valid_dec_to_rs : active high signal that the master device uses to indicate that the signal on the sample bus is valid [35:0] sample_dec_to_rs : the sample data written by the master devices
Functionality	The decimation block reduces the sampling rate to 48Ksps. The decimation factor is 25. Only 1 in 25 samples are kept, the other 24 samples are dropped.

<write up>

Rounding / Scaling

Module	Rounding / Scaling
Inputs	sample_valid_dec_to_rs : active high signal that the slave device uses to determine when the value on the sample bus is valid [35:0] sample_dec_to_rs : the sample data to be read by the slave device sample_rdy_o : active high signal that the master device uses to determine if the slave is ready to receive a sample sample_ack_o : active high signal that the master device uses to determine if the slave successfully received the sample rst : synchronous, active high reset signal en : synchronous, active high enable signal clk : system clock
Outputs	sample_rdy_rs_to_dec : active high signal that the slave device uses to indicate it is ready to receive a sample sample_ack_rs_to_dec : active high signal that the slave device uses to indicate that the sample has been successfully received sample_valid_o : active high signal that the master device uses to indicate that the signal on the sample bus is valid [17:0] sample_o : the sample data written by the master devices
Functionality	The purpose of the round / scaling block is to reduce the bit width of the samples from 36 bits down to 18 bits. The goal is to minimize the loss of information (non audible modifications are desired)

<write up>